In some high speed data links, digital data streams are sent from one communications node to another without an accompanying clock signal. Clock and Data Recovery (CDR) circuits are therefore utilized to recover data and timing information from a received signal. Typically, the CDR will extract a clock from the received signal, predict the location of the center of an “eye” diagram and sample data from the predicted center of the eye. Accordingly, there is a need to measure the timing margin of the CDR so that a manufacture or user, can characterize the performance of the CDR, and its effect on bit error rate (BER).
If the CDR is not functioning accurately, it leads to increased bit errors during data recovery because the data is not being sampled in the center of the eye. It is important for an end-user utilizing a particular CDR to know how well the CDR functions in terms of accuracy, and its timing margin before the CDR fails. For example, in a 5 GHz transmission system, the data or an eye may be 200 picoseconds wide and the CDR should be sampling in the middle. However, if the CDR samples off-center, then the probability of bit errors due to noise, etc., increases the farther the CDR samples from the center of the eye diagram. Timing margin characterizes how close to the center of the eye the data is being sampled. If the CDR is well centered, the system should be able to withstand a move of the phase (i.e. sampling time) to the left or the right from center, and still function with acceptable BER, indicating that the system has a good timing margin.
In a typical approach to measuring timing margin, a main detector operates in a primary data path, and a second detector is utilized in a secondary data path, which is operating in parallel with the primary data path. The main detector recovers data and the second detector is utilized to estimate the timing margin. Essentially, data is recovered from the first data path by sampling the data at the center of the eye (or as close to it as can be achieved). A second data path having the second detector simultaneously samples the same data. However, a phase offset is deliberately added to the sampling time of the second detector so as to sampling performed offset from the center of the eye diagram, relative to the first detector. After receiving the results of the first path and the second path, the user is able to compare the sampled results and determine the phase offset that results in an unacceptable BER, which then defines the timing margin. A disadvantage of this approach is the need for two separate data paths and the requisite duplicate hardware. Another typical approach entails the use of one path for clock recovery and another path for data recovery. The similar disadvantage for this approach is the need for at least partially duplicate hardware in such a system.
What is needed is an apparatus and method for measuring timing margin that does not require duplicate hardware.
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